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Alif Semiconductor /AE512F80F5582AS_CM55_HP_View /I3C /I3C_SDA_HOLD_SWITCH_DLY_TIMING

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Interpret as I3C_SDA_HOLD_SWITCH_DLY_TIMING

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SDA_TX_HOLD

Description

SDA Hold and Mode Switch Delay Timing Register

Fields

SDA_TX_HOLD

This field controls the hold time (in term of the CORE_CLK periods) of the SDA with respect to the SCL edge in FM, FM+, SDR and DDR mode of operations. The valid values are from 0x1 to 0x7. Others are Reserved.

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data